Circuits utilized for transmitting video signals over video cables should to be able to convert the video signals into a form suitable for driving 75 ohm or 150 ohm video cables with a high degree of accuracy, should perform a differential input voltage to single-ended output voltage conversion and should provide an appropriate quiescent DC output voltage.
A conventional circuit for performing differential to single-ended conversion is illustrated in FIG. 1. A differential input voltage is applied across the terminals Vinn1 and Vinp1. The terminal Vinn1 is coupled to a non-inverting input of an operational amplifier U1. An output of the operational amplifier U1 is coupled to a first terminal of a resistor R1 and to a first terminal of a resistor R2. A second terminal of the resistor R2 is coupled to a first terminal of a resistor R3 and to an inverting input of the operational amplifier U1. A second terminal of the resistor R3 is coupled to an inverting input of an operational amplifier U2 and to a first terminal of a resistor R4. A non-inverting input of the operational amplifier U2 is coupled to the terminal Vinp1. An output of the operational amplifier U2 is coupled to a second terminal of the resistor R4 and to a first terminal of a resistor R5. A second terminal of the resistor R5 is coupled to a first terminal of a resistor R6 and to an non-inverting input of an operational amplifier U3. A second terminal of the resistor R6 is coupled to a reference voltage Vref1. A second terminal of the resistor R1 is coupled to a first terminal of a resistor R7 and to an inverting input of the operational amplifier U3. An output of the operational amplifier U3 is coupled to a second terminal of the resistor R7 and to a terminal Vout1. A single-ended output voltage is formed at the node Vout1.
The circuit illustrated in FIG. 1 has a disadvantage in that it requires three separate operational amplifiers U1, U2 and U3, each of which can contribute to offset errors, signal distortion, and supply injection errors. The circuit illustrated in FIG. 1 is also subject to common-mode errors, particularly when the output stage resistors are not perfectly matched. Generally, a large input stage gain is required to minimize the common-mode gain sensitivity of the output stage. Gain accuracy can be poor, however, as several resistors must track each other.
Another circuit of the prior art for performing differential to single-ended conversion is illustrated in FIG. 2. A differential voltage is applied across the terminals Vinp2 and Vinn2. The terminal Vinp2 is coupled to a non-inverting input of a differential input to differential output transconductance amplifier U4. The terminal Vinn2 is coupled to an inverting input of the transconductance amplifier U4. A non-inverted output of the transconductance amplifier U4 is coupled to a non-inverting input of a current differencing amplifier U5. An inverted output of the transconductance amplifier U4 is coupled to an inverting input of the current differencing amplifier U5. An output of the current differencing amplifier U5 is coupled to an inverting input of an operational amplifier U6 and to a first terminal of a resistor R8. A non-inverting input of the operational amplifier U6 is coupled to a reference voltage Vref2. A output of the operational amplifier U6 is coupled a second terminal of the resistor R8 and to a terminal Vout2. A single-ended voltage is formed at the terminal Vout2.
The circuit illustrated in FIG. 2 has a drawback in that differential input to differential output transconductance amplifiers, such as the transconductance amplifier U4, often have poor gain accuracy and poor gain linearity due the emitter resistance of bipolar transistors utilized in the amplifier, as explained below with reference to FIG. 3. This effect can be offset somewhat by increasing biasing currents in the input stage of the transconductance amplifier U4, however, this results in higher power consumption and higher power dissipation. Further, current differencing amplifiers, such as the current differencing amplifier U5, generally utilize an asymmetrical set of current mirrors. Such current mirrors can introduce Early voltage effects, other systematic errors, and non-systematic matching errors.
A schematic diagram of a prior art differential input to differential output transconductance amplifier, such as the transconductance amplifier U4, is illustrated in FIG. 3. A supply node Vcc, is coupled to a source of a PMOS transistor M1, to a source of a PMOS transistor M2, to a source of a PMOS transistor M3 and to a source of a PMOS transistor M4. A drain of the transistor M1 is coupled to a gate of the transistor M1, to a gate of the transistor M2 and to a collector of an npn bipolar transistor Q1. A drain of the transistor M4 is coupled to a gate of the transistor M4, to a gate of the transistor M3 and to a collector of an npn bipolar transistor Q2. An emitter of the transistor Q1 is coupled to a first terminal of a bias current source Ibias1 and to a first terminal of a resistor Rgm1. An emitter of the transistor Q2 is coupled to a first terminal of a bias current source Ibias2 and to a second terminal of the resistor Rgm1. The input terminal Vinp2 is coupled to a base of the transistor Q1 and the input terminal Vinn2 is coupled to a base of the transistor Q2. A second terminal of the bias current source Ibias1 and a second terminal of the bias current source Ibias2 are coupled to the ground node.
An output current Ioutp2 is formed at a drain of the transistor M2 and an output current Ioutn2 is formed at a drain of the transistor M3. The transistor Q1 and Q2 act as voltage followers. The collector current in the transistor Q1 is mirrored by the transistors M1 and M2 to form the output current Ioutp2. The collector current in the transistor Q2 is mirrored by the transistors M3 and M4 to form the output current Ioutn2. An ac differential in the input voltages results in an ac differential in the output currents.
Ideally, for a differential input to differential output transconductance amplifier, the differential output currents are given the .+-.igm=(Vinp2-Vinn2)/Rgm1. In the circuit illustrated in FIG. 3, however, due to the small signal r.sub.e of Q1 and Q2, the actual differential output currents are given by .+-.igm=(Vinnp2-Vinn2)/(Rgm1+2r.sub.e). The resistance r.sub.e is the emitter resistance of each of the transistors Q1 and Q2, which varies inversely with the current through each of the transistors Q1 and Q2. Therefore, the gain of the amplifier illustrated in FIG. 3 is non-linear because the emitter resistances r.sub.e change with the load currents into Rgm1 which transit through the transistors Q1 and Q2, and, thus, the emitter resistances r.sub.e change with the input voltages. The effect of changes in r.sub.e can be reduced by significantly increasing the device sizes and bias currents. This is not an entirely satisfactory solution, however, because large device sizes require significant silicon space and high bias currents result in increased power consumption and increased power dissipation in the amplifier.
FIG. 4 illustrates a schematic diagram of a prior art Norton amplifier with feedback. An input terminal Iinn3 is coupled to a base of an npn bipolar transistor Q3, to an anode of a diode D1 and to a first terminal of a resistor R9. An input terminal Iinp3 is coupled to a base of an npn bipolar transistor Q4 and to a collector of the transistor Q3. A supply node Vcc is coupled to a first terminal of a current source Ibias3. A second terminal of the current source Ibias3 is coupled to a collector of the transistor Q4, to an output terminal Vout4 and to an input terminal of a unity gain, inverting amplifier U7. A second terminal of the resistor R9 is coupled to an output of the amplifier U7 and to an output terminal Vout3. A cathode of the diode D1, an emitter of the transistor Q3 and an emitter of the transistor Q4 are coupled to a supply node Vss.
The amplifier illustrated in FIG. 4 forms a single-ended output voltage vout3 at the output terminal Vout3 given by: vout3=(iinp3-iinn3)(R9) where iinp3 and iinn3 are ac currents applied to the terminals Iinp3 and Iinn3, respectively. This circuit has a drawback in that it has an asymmetrical architecture and requires base currents for each of the transistors Q3 and Q4. As a result, the output voltage vout3 can include common-mode errors and the gain of the circuit tends to be non-linear. In addition, this architecture is somewhat inflexible because the input terminals Inn3 and Inp3 are held at one base-emitter junction voltage above the level of Vss and the output voltage vout3 has a quiescent value that is approximately one base-emitter junction voltage above the level of Vss. Further, base-emitter junction voltages vary with bias current, which can adversely affect the output voltage vout3.
FIG. 5 illustrates a schematic diagram of an input stage of a prior art current mode feedback operational amplifier. A supply node Vcc is coupled to a collector of an npn bipolar transistor Q5, to a first terminal of a bias current source Ibias4 and to a first terminal of a bias current source Ibias6. An emitter of the transistor Q5 is coupled to a first terminal of a bias current source Ibias5 and to a base of a pnp bipolar transistor Q6. A second terminal of the current source Ibias5 is coupled to a supply node Vss. A second terminal of the bias current source Ibias6 is coupled to an emitter of a pnp bipolar transistor Q7 and to a base of an npn bipolar transistor Q8. An emitter of the transistor Q8 is coupled to a first terminal of a bias current source Ibias7, to a second terminal of the bias current source Ibias4, to an emitter of the transistor Q6 and to an input terminal Iinn4. A collector of the transistor Q7 and a second terminal of the bias current source Ibias 7 are coupled to the supply node Vss. A base of the transistor Q5 and a base of the transistor Q7 are coupled to an input terminal Iinp4. A collector of the transistor Q6 is coupled to an output terminal Ioutn4 and a collector of the transistor Q8 is coupled to an output terminal Ioutp4.
The complementary push-pull emitter-followers of FIG. 5 tend to force any input currents applied to the terminals Iinp4 and Iinn4 to be equal. Any difference between the input currents results in a pair of differential output currents at the terminals Ioutn 4 and Ioutp4. The output currents can be coupled to an output stage (not shown) to form an output voltage. The amplifier illustrated in FIG. 5 suffers from a drawback in that it is limited to a relatively small input signal range and its practicality is limited because its manufacture requires a fully complementary bipolar process.